The invention applies more particularly to a system for designing digital circuitry comprising:                a digital circuit simulator based on a file containing a functional description of this digital circuit,        means for estimating an output variable from the digital circuit when executing a test bench supplied to the simulator,        event counters, the events being detected using control signals provided by the simulator when executing the test bench.        
The event counters form an activity sensor for the simulated digital circuit. It is known to use data supplied by such a sensor to calculate, using a model yet to be defined, an actual output variable in the circuit, such as power consumption, released temperature, etc. Thus, by knowing the successive values of the output variable given by the simulation and data supplied by the event counters, it is known to build a model to calculate this output variable by linear regression. This model can then be implemented, using a monitor (to capture current activity) and a calculator (to apply the model) in the actual circuit that was previously simulated. The benefit of such a calculation is that it reports the circuit's activity based on implemented programs and adjusts the circuit's effort in dynamic control loops. The output from the calculation model can then feed into a regulation system that adjusts the frequency of the circuit's functional blocks and their voltage to optimize the estimated variable.
A problem arises when we want to apply such a model for calculating an output variable to a complex digital circuit, such as a system-on-chip (SoC) design. Because the surface of such a circuit is generally limited, it becomes necessary to make a selection on the control signals and hence on the event counters. Usually, the selection is done intuitively based on prior knowledge of the architecture. However, this is a tedious task that becomes complicated with the increasing complexity of the SoC.